1. Field of the Invention
This invention relates to SET-RESET latch circuits which produce logic latched outputs determined by SET and RESET inputs.
2. Description of the Related Art
Various types of circuits have been developed that produce and hold output states in response to input pulses. These include standard cell D-type flip-flop circuits with a clear (an example is the Motorola, Inc. MECL 10K circuit, described in MECL DATA by Motorola, Inc., 1996, page 1-5), the standard cell S-R (SET-RESET) latch (an example is described in Analog Devices, "ADRF ECL Cell Library Datasheet", 1996, and the solid state integrated logic flip-flop or S-R latch in Taub and Schilling, "Digital Integrated Electronics", McGraw-Hill, Inc., 1977, pages 278283.
Each of these circuits exhibits a degree of undesirable jitter and settling time in responding to control inputs. This lowers their bandwidth and makes the logic output lag undesirably behind the application of the control input.